Transcript SystemC_4-1.ppt

Reactivity, Ports, and Signals
in SystemC
Part of
HW/SW Codesign of Embedded
Systems Course (CE 40-226)
Winter-Spring 2001
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Today programme
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Concept of Reactivity
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Reactivity facilities in SystemC
Ports and Signals in SystemC
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Resolved Logic Vectors
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Reactivity, Ports, and Signals
in SystemC
Reactivity Modeling
in
SystemC
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Concept of Reactivity
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Property of Reaction to external events
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Inherent in HW => There MUST be some way to
model it in any HDL
Many SW or HW-SW systems are reactive as well:
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Any control systems (Chemical process control, ABS, …)
Client-Server systems (Database Engines, …)
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Concept of Reactivity (cont’d)
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Things to consider
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Events to react to
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Type of event (Clock edge, Signal change, some
condition on signals or ports, …)
Style of reaction
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Waiting style
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Suspend process until an event comes or some condition
holds (i.e. Blocking wait)
Watching style
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Do not suspend. But always WATCH if some condition
holds. Then, react accordingly: e.g. Jump to a certain
routine, or point of a routine. (Non-blocking wait)
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Reactivity Facilities
in SystemC
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Events to react to
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Sensitivity lists in SC_METHOD, SC_THREAD. And
clock edge in SC_CTHREAD.
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Sensitivity to any event on a signal: sensitive data
member of SC_MODULE
Sensitivity to positive edge of a signal: sensitive_pos
data member of SC_MODULE
Sensitivity to negative edge of a signal: sensitive_neg
data member of SC_MODULE
Special case of infinite loop processes
(SC_THREAD, SC_CTHREAD)
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Loop re-initialization, Wait for Signal condition
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Reactivity Facilities
in SystemC (cont’d)
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Style of reaction
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Waiting style
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wait()
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wait_until(<signal condition>)
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Both SC_THREAD and SC_CTHREAD
Only SC_CTHREAD
Watching style
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Global watching: Always done. Cannot be disabled.
Local watching: Done in certain parts of a process. Can
be disabled and re-enabled (statically)
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Global Watching Example
SC_MODULE(data_gen) {
sc_in_clk clk;
sc_inout<int> data;
sc_in<bool> reset;
void gen_data();
SC_CTOR(data_gen){
SC_CTHREAD(gen_data,
clk.pos());
watching(reset.delayed());
}
};
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void gen_data() {
if (reset == true)
data = 0;
}
while (true) {
data = data +
wait();
data = data +
wait();
data = data +
wait();
}
}
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1;
2;
4;
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Global Watching in General
void data_gen::gen_data () {
// variable declarations
// watching code
if (reset == true) {
data = 0;
}
// infinite loop
while (true) {
// Normal process function
}
}
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Local Watching in General
W_BEGIN
// put the watching declarations here
watching(...);
watching(...);
W_DO
// This is where the process functionality goes
...
W_ESCAPE
// This is where the handlers for the watched events
// go
if (..) {
…
}
W_END
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Local Watching Example
void bus::xfer() {
while (true) {
// wait for a new address to
// appear
wait_until(
newaddr.delayed() == true);
// got a new address so
//process it
taddr = addr;
datardy = false;
// cannot accept new address
// now
data8 = taddr.range(7,0);
start = true; // new addr
// for memory controller
wait();
// wait 1 clock between data
// transfers
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data8 = taddr.range(15,8);
start = false;
wait();
data8 = taddr.range(23,16);
wait();
data8 = taddr.range(31,24);
wait();
// now wait for ready signal
// from memory
// controller
wait_until(ready.delayed()
== true);
W_BEGIN
watching(reset.delayed());
// Active value of reset
// will trigger watching
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Local Watching Example
(cont’d)
W_DO
// the rest of this block is
// as before
// now transfer memory data
// to databus
tdata.range(7,0) =
data8.read();
wait();
tdata.range(15,8) =
data8.read();
wait();
tdata.range(23,16) =
data8.read();
wait();
tdata.range(31,24) =
data8.read();
data = tdata;
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datardy = true; // data is
// ready, new addresses ok
W_ESCAPE
if (reset) {
datardy = false;
}
W_END
}
}
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HW Design Using
SystemC
Ports and Signals
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Ports and Signals Outline
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Port and Signal Usage
Port Declaration
Signal Declaration
Valid Interconnections
Special Objects: Clocks
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Port and Signal Usage
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Port
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Module’s Interface to external world
Signal
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Connect Modules’ ports together
Convey values between ports (and hence modules)
Module1
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Signal
Module2
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Port Declaration
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Things to declare
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Port Mode
Port Type
Port Name
Declaration Syntax
Port_mode<Port_type> Port_name [, Port name, …];
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Port Declaration
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Things to declare
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Port Mode
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Input:
sc_in
Output:
sc_out
Bi-directional(inout): sc_inout
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Port Declaration
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Things to declare
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Port Mode
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Input:
sc_in
Output:
sc_out
Bi-directional(inout): sc_inout
Port type
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C++ built-in type, SystemC types, and User defined types
Scalar, and Array ports
Special case: Resolved Logic Vector
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Port Declaration
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Things to declare
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Port Mode and Type
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Port Type
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Input:
sc_in
Output:
sc_out
Bi-directional(inout): sc_inout
C++ built-in type, SystemC types, and User defined types
Scalar, and Array ports
Special case: Resolved Logic Vector
Port Name
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Any valid C++ identifier
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Port Types
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C++ built-in types
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M1
long, int, char, short, float, double
SystemC types
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sc_int<n>, sc_uint<n>, sc_bigint<n>, sc_biguint<n>, sc_bit,
sc_logic, sc_bv<n>, sc_lv<n>, sc_fixed, sc_ufixed, sc_fix,
sc_ufix
User defined types
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sc_in<int> i
Scalar Types
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struct, class, typedef, enum
Array types
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Declares an array of ports
sc_in<int> i[10]
Each port must be individually
bound, assigned, read, and written
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Port Types (cont’d)
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Special case: Resolved Logic Vectors
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Usage
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Multi-driver ports (e.g. Buses)
Resolution function:
 z and 0  0
 z and 1  1
 0 and 1  x
 x and (1 or 0 or x or z)  x
Declaration syntax
sc_in_rv<n> port_name [, port_name, …];
sc_out_rv<n> port_name [, port_name, …];
sc_inout_rv<n> port_name [, port_name, …];
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Signal Declaration
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Things to declare
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Signal type
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Signal name
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The same as port types
Special case: Resolved vector signals
Any valid C++ identifier
Declaration syntax
sc_signal<signal_type> sig_name [, sig_name, …];
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Signal Types
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The same as port types
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Scalar
Array Signals
Special Case: Resolved Logic Vectors
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Declaration syntax
sc_signal_rv<n> sig_name [,sig_name, …];
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Valid Interconnections
Signals required
M1
M2
Higher-Level Module
Undocumented:
Exceptions at least
include:
positional mapping
M1
Direct Connection
No Signal required
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Valid Interconnections (cont’d)
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Port reading and writing
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Reading a port = taking value of the signal bound
to the port
Writing a port = writing new value to the signal
bound to the port, but AFTER the writing process
has exited or been suspended
Signal binding
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Each port to a single signal
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Repetitive bindings of a port  FIRST binding will remain
effective
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Special Objects: Clocks
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Clocks generate timing signals to synchronize
simulation events
No clock-signal is declared
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Instead, and sc_clock object is instantiated
Declaration syntax
sc_clock clk_name(“clk_name”, clk_period=1,
clk_duty_cycle=0.5,
first_edge_time=0,
first_edge_type=true);
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Special Objects: Clocks
(cont’d)
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Multiple clocks are allowed
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Different frequencies
Different phase relations
Declaration point
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Typically generated at top-level module and
passed down to lower-level modules
The clock object or its signal (i.e.
clock_object.signal() ) can be passed down
SC_CTHREAD modules need the clock object itself
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sc_in_clk clk_object_name;
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Special Objects: Clocks
(cont’d)
sc_clock clock("Clock", 20, 0.2, 3, false);
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What we learned today
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Reactivity
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Concept
SystemC facilities to model reactivity
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wait, wait_until
global watching, local watching
Ports, Signals, and Clocks in SystemC
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Complementary notes:
Assignments and Project
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Today is due date for Assignment 5
Take Assignment 6
Due date: Sat. Ordibehesht 15th
Today is due date for Page-of-References of
your project
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Complementary notes:
Extra classes
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“HW Synthesis Techniques Seminar” by S. Safari
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Date-Time: TODAY, 13 O’clock
Place: Kwarizmi Hall, CE Dept.
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