Automated Synthesis and Modeling of Analog and Mixed-Signal Systems

Alex Doboli, PhD Associate Professor Department of Electrical and Computer Engineering State University of New York, Stony Brook, NY 11794 Email: adoboli@ece.sunysb.edu

Mixed-Domain Embedded Systems Laboratory

(http://www.ece.sunysb.edu/~vsdlab ) •

Analog and mixed-signal synthesis:

–

Heuristic optimization algorithms (many kinds)

–

Integer linear and nonlinear programming

–

Synthesis from VHDL-AMS

•

Automated modeling for design:

–

Automated modeling of analog circuits and systems

–

Modeling of process parameter variations

– – – –

Linear and nonlinear symbolic methods Statistical modeling Compiled code simulation Neural networks and PWL modeling

Mixed-Domain Embedded Systems Laboratory

(http://www.ece.sunysb.edu/~vsdlab ) •

Synthesis of analog and mixed-signal circuits with high degree of innovation:

–

Understand the difference between human designed circuits and automatically synthesized circuits

–

Understand the level of innovation of new design solutions

–

Representation of design knowledge for innovation:

•

Classification scheme to show commonalities and differences

•

Management and reuse of existing IP

–

Synthesis method using the representation:

•

Process more similar to human design process (i.e. combination of existing design features)

Automated synthesis of analog and mixed signal systems VHDL-AMS specifications:

entity aaa is … end entity;

Circuit and interconnect models Performance evaluation (simulation) Topology generation and system architecture selection: integ integ m m DAC m Constraint transformation , floorplanning and global routing Performance evaluation Obtained performance

Application-specific

DS

modulator topologies

H. Tang, A. Doboli, "

Consumption" High-Level Synthesis of Delta-Sigma Modulators Optimized for Complexity, Sensitivity and Power

, IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 25, No. 3, pp. 597-607, 2006.

•

Automatically synthesize

DS

modulator topologies optimized for a given application (specification)

•

Novelty :

• •

Synthesis methods for topology (no general method available) New theoretical formulation

•

Advantages :

•

Global optimal solution is guaranteed (new topologies invented)

• •

The methodology is scalable The methodology could be fully automated

Generic topology for 3 rd order modulator Chain of Integrators with Feedforward Summation Chain of Integrators with Distributed Feedback, Distributed Feedforward and Local Feedback Generic topology Chain of Integrators with Distributed Feedback

Optimal topology Minimum signal path (topology not unique)

9 signal paths 9 signal paths

Optimal topology Minimum sensitivity

Sensitivity cost function values are 1.723 and 2.250

S x i

,

S x i

 1 .

0 L. Huelsman, “Active and Passive Analog Filter Design”, McGraw Hill, 1993

Topology from Toolbox Sensitivity cost function values is 4.454, with some terms larger than 1.0, e.g.

S q

3

a

3 ,

S q

3

t

34  1 .

0 R. Schreier, “The Delta-Sigma Toolbox 6.0”, www.mathworks.com/matlabcentral/fileexchange, Nov 2003.

Synthesis of Reconfigurable

DS

Modulators

Y. Wei, H. Tang, A. Doboli, "Systematic Methodology for Designing Reconfigurable Delta Sigma Modulator Topologies for Multimode Communication Systems", invited paper, IEEE Transactions on CADICS, Vol. 26, No. 3, March 2007.

A cell phone chip works for CDMA, GSM, UMTS … … •

Design Specifications

Mode UMTS CDMA2000 GSM EDGE DR (bits/dB) 11.5/70 13/80 15/90 14.5/87 Bandwidth 1.92MHz

615kHz 190kHz 270kHz

Reconfigurable

DS

modulator topologies Topology opt1

Experiments

•

Compare the triple-mode modulator with three single mode modulators obtained with

DS

toolbox

–

Design effort can be less than 1/3

–

Complexity can be as less as 40%

–

Power saving can be as large as 24.2%

–

More robust to circuit nonidealities

SNR degradation due to circuit noise

Improvement as compared to the state-of-art design: 3dB for the case of -60dB noise level 5dB for the case of -50dB noise level

Experiments

Algorithms for Analog Synthesis

H. Tang, H. Zhang, A. Doboli, "Refinement based Synthesis of Continuous-Time Analog Filters Through Successive Domain Pruning, Plateau Search and Adaptive Sampling", IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 25, No. 8, pp. 1421-1440, 2006.

3 rd order elliptic lowpass filter Synthesis problem : – Find circuit constraints and system parameters so that functionality is achieved, and multiple performance attributes are optimized

Slow convergence Plot 3 Plot 1 Cost=3000

oscillation

Large sampling steps (20,20 sec)

plateau

Cost=6 Plot 2 Convex region Small sampling steps (5,000,6hours)

• Plot 1 • Plot 3 : smaller variable ranges is good • Plot 2: different types of regions: convex regions mixed with plateaus : adaptive sampling for buried optima

Experiments NeoCircuit Circuit Explorer Plateau search

Small ranges Large ranges Time Total # Separ. Total # Separ. (hrs) Small ranges Large ranges Total # Separ.

Total# Separ.

Time (hrs) Large ranges Total # Separ.

Time (hrs) 3 rd (12M) 23 3

13 3

1.6

49 5

28 1

6.3

40 11

6.3

3 rd (100M) 17 3 4 th 38 7 5 th 80 3

7 0 1 18 3

6.0

22 3

12 0

1.6

16 18 47 2 1

0 2 0 3 1

6.3

19

11 20 5 2

6.3

15

27 11

15 19

Experiments (

DS

ADC)

3 rd order SD 4 th order SD

SA Plateau search

Very good good fair Time (hrs) Very good good fair Time (hrs) 0 1 2 51 1 3 7 87 0 1 3 53 2 5 11 98

Automated Macromodeling

Y. Wei, A. Doboli, "Structural Macromodeling of Analog Circuits through Model Decoupling and Transformation", IEEE Transactions on CADICS, Vol. 27, No. 4, April 2008.

•

Produced macromodels:

– – – – – –

Structural No feedback dependencies (decoupled) Symbolically characterized nonlinear current sources Extensible, accuracy is controllable Insight into circuit Reusable

Automated Macromodeling

Circuit netlist Structural nonlinear macromodel (R 2 ,C 2 ) v in f(v in ) v out Black-box macromodel

Automated Macromodeling

Circuit netlist

Automated Macromodeling

Comparison of HD2, HD3

Automated Macromodeling

Automated Macromodeling

Automated Macromodeling

Automated Macromodeling

Process Variation Modeling

H. Zhang, A. Doboli, "A Scalable Sigma-Space Based Methodology for Modeling Process Parameter Variations in Analog Circuits", Microelectronics Journal, Elsevier, February 2009.

The limitation of the



SA Method

3 4 5 6 Index 1 2 Iref  SA Iout D I Iref ALAMO Iout D I 0.0156

0.0398

0.0366

0.0270

0.0357

0.0362

0.0159

0.0391

0.0358

0.0273

0.0351

0.0363

0.0160

0.0393

0.0362

0.0273

0.0353

0.0365

0.0277

0.0208

0.0364

0.0276

0.0346

0.0361

0.0273

0.0274

0.0208

0.0211

0.0356

0.0360

0.0272

0.0274

0.0353

0.0353

0.0363

0.0365

P i

 

a

1

i a

2

i



a Ni



R

1

R

2 

R N

 T ,

R n

: unit normal number “ Statistical

Christopher

Modeling for Computer-Aided Design of MOS VLSI Circuits”, Michael and Mohammed Ismail, Kluwer Academic Publishers, 1993

Process Variation Modeling Method

Experimental Results

Experimental Results

Modeling and Fast Simulation of Nonlinear Systems

H. Zhang, S. Doboli, H. Tang, A. Doboli, "Compiled Code Simulation of Analog and Mixed-Signal Systems Using Piecewise Linear Modeling of Nonlinear Parameters", Integration the VLSI Journal, Elsevier, Vol. 40, No. 3, pp. 193-209, 2007.

• At the system-level, the method uses symbolic descriptions of ADCs • Building blocks are macromodels, which include circuit non-idealities and nonlinear behavior. • Non-linear parameters are expressed using PWL models, which are created automatically through model extraction from trained neural networks (NN) .

• Method is more accurate than simulation of behavioral models • Method is significantly faster than numerical simulation (two orders of magnitude) • Accuracy is not traded-off for speed • Simulator code can be optimized to avoid convergence problems

Simulation Methodology - overview Topology PWL MM library Model abstraction Level selection Modified nodal analysis Terminal block analysis DDDs PWL segment control flow generation Connection pattern recognition Lazy generation of symbolic expression APTs GIT library Middle block analysis Code generation Code optimization Compiled-code simulator Code generation and optimization

Structure of 3 rd -order Single-loop

S

-

D

Modulator

Simulation Results

SD

ADC order

1 2 3 4 5

Spectre + VerilogXL(s )

507.1

533.9

852.3

1284.9

1752.0

Symbolic (s)

3.5

5.88

8.24

10.69

12.91

Speed-up

144.88

90.79

103.43

120.19

135.70

Comment: Because of the extreme values of some parameters, we had severe convergence problems in Cadence Mixed-Signal Simulation Environment (Spectre + Verilog A).

Conclusions

•

Automated synthesis of analog and mixed-signal synthesis:

–

Heuristic optimization algorithms (all kinds)

–

Integer linear and nonlinear programming

–

Stochastic methods (Markov chains, dynamic programming)

•

Automated modeling for design:

–

Automated modeling of analog circuits and systems

–

Modeling of process parameter variations

– – – –

Linear and nonlinear symbolic methods Statistical modeling Compiled code simulation Neural networks and PWL modeling

Towards Creative Analog Synthesis: A Symbolic Representation for Exploring Circuit Operation Principles

Cristian Ferent

and

Alex Doboli

cferent@ece.sunysb.edu

Motivation, Goals, and Contributions



Systematically characterize a collection of designs :

   

Implement performance specific circuit models Highlight common & different features between circuits Identify advantages & limitations of a circuit compared to others Derive conditions under which design alternatives exhibit similar performance

Motivation, Goals, and Contributions (II)



Model to characterize transconductor linearity



Illustrate mechanisms which can enhance circuit performance: extended operating range and/or device non-linearity compensation

Motivation, Goals, and Contributions (III)



Automatically produce circuit classification schemes :



Build a model to express main similarities & differences between a set of circuits implementing the same functionality



Based on topological structures of features that influence the performance of a design



Produce compact classification – minimum of separation criteria

Problem Description: concept representation

Coupling between nodes Features related to performance Classification along curve D 1 Distinguishing criteria curves Circuit node Similar node features

C. Ferent, A. Doboli, "A Symbolic Technique for Automated Characterization of the Uniqueness and Similarity of Analog Circuit Design Features", DATE 2011

Proposed Method: automated generation of classification schemes

  

Produce the separation criteria for a given performance Determine best separation criteria Construct hierarchical classification scheme

Algorithm Details

1) Build performance-based circuit models 2) Group nodes with similar behavior:

  

Minimize total number of matched groups (N ) Minimize matching error within groups of nodes Identify constraints under which matching is valid

Algorithm Details (II)

3)

Sort matched groups :



Signal path tracing and model decoupling algorithms 4) Use entropy to rank similarities and differences between circuits:

 

N – number of circuits represented in cluster C k p i – probability a circuit from cluster C k matched group G j is associated with 5) Produce hierarchy with maximum matching at higher levels

AC Domain Model Matching: amplifier circuits hierarchical classification

Similar behavior Increasing entropy value Common structures Different structures Different behavior

Classification correlation with performance

Also identify number of terms that differ between node structures



Indication of topology’s flexibility to satisfy performance (e.g. setting pole and zero positions)

Transconductor Linearity Models

Extend range Correct linearity

Linearity Model Matching: transconductors hierarchical classification

Common structures Identical Processing Path Additional Processing Different structures

Linearity Model Matching: (II) transconductors hierarchical classification

Additional Control Additional Control Voltages Identical Control Path

Current Developments



Apply the proposed methodology for a set of 10 state-of-the-art amplifier designs



Derive topological and performance classification schemes

Conclusions



Develop new symbolic technique for automated generation of circuit classification schemes



Produce the set of separation criteria



Based on performance specific circuit models



Sort separation criteria based on their capability to distinguish between different structures



Proposed metric based on entropy



Build hierarchical classification



Highlight similarities and differences with impact on performance



Offer insight through symbolic expressions

  

Identify common & dissimilar circuit node structures Relate symbolic differences and similarities to performance attributes Suggest design’s flexibility for achieving certain performance