Transcript Cadence Opus course

Introduction to Cadence
Opus
Digital HDL design
NCVerilog
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Overview
The Cadence® NC-Verilog® simulator is a Verilog digital logic
simulator that combines the high-performance of native
compiled code simulation with the accuracy, flexibility, and
debugging capabilities of event-driven simulation.
In a Verilog/VHDL configuration, both the Verilog and VHDL
compilers are used to generate code for the Verilog and VHDL
portions of the design, respectively. During an elaboration
process (similar to the linking used in computer programming),
the Verilog and VHDL code segments are combined into a
single code stream. This single executable is then directly
executed by the host processor (simulator).
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
HDL simulation Design Flow
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Short verilog syntax summary
The basic structure of a Verilog description
`timescale …ns/…ps
module name(p1, p2, p3, ... pn);
input p1, p2;
input [msb1 : lsb1] p3;
output p4, p5;
output [msb2 : lsb2] p6;
...
...
Body of the module
...
...
endmodule
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The basic unit of a Verilog
description is the module
Delimited by module and
endmodule keywords
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Simple Verilog behavioral example
The simple example - RS Flip-Flop
`timescale 1ns/10ps
module rsl1(q, qn, preset, clear);
output q, qn;
input preset, clear;
wires q, qn
reg q, qn;
always @(preset or qn)
#1 q = !(qn && preset);
always @(clear or q)
#1 qn= !(q && clear);
endmodule
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In the body of the module
have to be declared the
input and output ports,
registers, wires …
The identifiers of the
registers can be used
similarly as input or output
ports of the module.
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Simple Verilog behavioral example
The simple example - RS Flip-Flop
The timescale determines the
`timescale 1ns/10ps
period of the time between two
module rsl1(q, qn, preset, clear);
steps for the simulator
output q, qn;
input preset, clear;
wires q, qn
reg q, qn;
always @(preset or qn)
#1 q = !(qn && preset);
always @(clear or q)
#1 qn= !(q && clear);
endmodule
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always (condition)
#n … What to do …
If there are any changes on the
input ports and the condition is true
then the procedure will be executed
In this example both always
procedures have unit delay (in this
case 10ns)
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Simple Verilog RTL example
The simple example - RS Flip-Flop
`timescale 1ns/10ps
module rsl2(q, qn, preset, clear);
output q, qn;
input preset, clear;
wire q, qn;
// declare two nand gates
// with unit delay
nand #1
g1(q, qn, preset),
g2(qn, q, clear);
endmodule
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The other possibility to
describe a structure is using
built-in generic gates (RTL
level description)
wires have to be declared
as connecting elements
between the parts of the
model
In this example two nand
gates defined by unit delay
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Generating Testbench
If the model of a circuit (or a function) has been constructed
then the next step is verifying it by simulation. For this
purpose a testbench is needed, which contains an instance
of the model and provides the stimuli (input test signals
sequence).
The testbench forms the external world for the model to be
tested. The driving signals have to be generated here as well
as the outputs of the model have to be received and, if
necessary, processed.
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Generating Testbench
The simple example - RS Flip-Flop testbench
`timescale 1ns/10ps
module rslx_test;
wire q, qn;
reg preset, clear;
parameter d = 10;
rsl1 latch(q, qn, preset, clear);
initial
begin
preset = 0; clear = 1;
#d preset = 1;
#d clear = 0;
#d clear = 1;
end
endmodule
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Declaration part of two output
wires, two input variables
(registers)
Create an instance of the
RS-FF modul (instance call)
Initial procedure
initial
begin
… runs only once …
end
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Verilog environment at here
• Operating System: Sun Sparc Solaris 2.7
• Windows System: Openwindows 3.5
• Program version: LDV 3.4 (s004)
• Specific to our site: there is a script for Verilog tool which
starts it with proper settings  suggest the same to your
Unix/CAD system administrator
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Verilog environment at here
• Set the unix environment variables
setenv CDS_INST_DIR /soft/opus/ldv34
setenv CDS_INSTALL_DIR /soft/opus/ldv34
setenv PATH $CDS_INST_DIR/tools/bin: $CDS_INST_DIR/tools/dfII/bin:
$CDS_INST_DIR/tools/simvisdai/bin:$PATH
setenv LD_LIBRARY_PATH $CDS_INST_DIR/tools/lib:$LD_LIBRARY_PATH
• Set Cadence license environment variable
setenv CDS_LIC_FILE license_file
• Check the special licenses!
Affirma_NC_Simulator
VERILOG-XL
VERILOG-SLAVE
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Coffee break
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Login into the workstation
Login: cadence
Password: cadence
Guest user
with full rights
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Start up NCVerilog
Middle click at an empty place
of the screen and the
Engineering Tools popup
window opens.
Make a left click on the
Simulators  Verilog/VHDL
This solution is site specific!
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Starting the Verilog tool
A new UNIX shell comes up and
asks for the Verilog home
directory, where the verilog
source files will be stored
If this directory doesn’t exist, it will
be created automatically (the
default name is NCHDL)
If you first run the Verilog tool the
program asks if you want Multiple
Step or Single Step procedure.
Choose Multiple Step item in
that dialog box
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Starting the Verilog tool
The multiple step process flow contains:
• Behavior model description generation of the units (modules)
• Compilation is analogous to that of computer programs.
Each module is taken one by one and translated into an
internal format (such as object files in computers)
• Elaboration does some kind of linking the modules with each
other to form a single code stream per unit
• Simulation of the elaborated objects
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Setting your environment
Determine the working
directory
In the menubar click
FileSet Design
Directory…
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Setting your environment
Click the Create cds.lib File…
Click Save button
Select the last
checkbox, and
press OK
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Setting your environment
The work library name automatically
entered, and in the main windows
similar directory structures can be
seen:
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Generating HDL description
The next step is to start writing the verilog source code(s)
First at all the text editor have to be selected
Select Edit  Preferences…
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Generating HDL description
The Editor Command can be
changed for textedit %F
or gvim %F
Then press OK button
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Generating HDL description
Create a new directory for HDL
sources
Enter the name of the directory
(e.g. sources) then press OK.
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Generating HDL description
Click FileEdit new File…
menu item in the main window
It shows the actual directory,
in most cases it is the recently
specified verilog home directory
The contents of the
directory be shown here
The file name of the verilog
source can be entered here
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Change directory to sources
(double click at sources), then
specify a verilog filename (e.g.:
alu.v) then click Save button and
the text editor opens …
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Generating HDL description
In the text editor the verilog
source can be entered
To save the code push the
right button onto the File
and select Save then
release right button.
When finished close the
window
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Compiling Verilog sources
To compile the sources
click on the Vlog button
or
Select ToolsVerilog
Compiler menu item
Compiling the verilog
sources generates the
new modules in the
module window like
some subentries of our
worklib
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Elaborating compiled module
Select highest
hierarchical level
module of the
testbench
CLICK on the
Elaborate button
or
Select
ToolsElaborator
menu item
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Elaborating compiled module
At the first elaboration select
the ToolsElaborator
menuitem which invokes the
Elaborate dialog box
The Access Visibility should be
set to all and should be
checked !!!
Then press OK button
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Simulating code stream
After elaboration the
Snapshots folder can be
opened in the module
panel
Select the snapshots
and click on the
Simulate button
or
Select
ToolsSimulate menu
item
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Simulating code stream
The new window
(ncsim simulator
windows) be opened
Left click Select 
Signals in the menu
bar
In the source code
the all signals appear
highlighted
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Simulating code stream
Left click Waveform
button
The waveform
window appears
Click the big “play”
button  to Run
Simulation
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Simulating code stream
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Simulating code stream
In the waveform windows at the upper left corner there are a
small red flags of the cursors. They can be dragged by the left
and the middle mouse button. In the narrow pane between the
signal list and the waveform the signal values can be read, at
the simulation time indicated by the cursor TimeA.
For simple zoom facility hold down the right mouse button on
the waveform and a simplest zoom menu appears
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Simulating code stream
Displaying internal signals
By clicking right of the
Subscopes box at the
small button with the
black
triangle
a
dropdown list appears
showing the internal
modules
of
the
simulated system
Selecting one of them
the actual source code
text appears in the
source code pane.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Simulating code stream
Displaying internal signals
If all the signals of the
internal module are
needed to display,
then them can be
selected
by
left
clicking at Select>Signals
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Break!
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study I
Arithmetical Logical Unit (ALU)
The center core of a central processing unit, performs a set
of arithmetic and logic micro operations
Generate a behavior Verilog description of ALU
Sel[4:0]
Sel[1:0]
A[7:0]
B[7:0]
Sel[2]
Logic
Unit
Logic Unit [7:0]
MUX
ALU_noShift[7:0]
Arith Unit [7:0]
Carryin
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Sel[4:3]
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Shifter
Case study I
Arithmetical Logical Unit (ALU)
It has n encoded inputs for selecting which operation to perform
S4
0
0
0
0
0
0
0
0
S3
0
0
0
0
0
0
0
0
S2
0
0
0
0
0
0
0
0
S1
0
0
0
0
1
1
1
1
S0
0
0
1
1
0
0
1
1
Cin
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
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Operation
Y <= A
Y <= A + 1
Y <= A + B
Y <= A +B + 1
Y <= A + Bbar
Y <= A + Bbar + 1
Y <= A - 1
Y <= A
Function
Transfer A
Increment A
Addition
Add with carry
A plus 1's complement of B
Subtraction
Decrement A
Transfer A
0
0
0
0
Y <= A and B
Y <= A or B
Y <= A xor B
Y <= Abar
AND
OR
XOR
Complement A
Logic Unit
Logic Unit
Logic Unit
Logic Unit
0
0
0
0
Y <= A
Y <= shl A
Y <= shr A
Y <= 0
Transfer A
Shift left A
Shift right A
Transfer 0's
Shifter Unit
Shifter Unit
Shifter Unit
Shifter Unit
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Implementation block
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Case study I
Arithmetical Logical Unit (ALU)
In the beginning define the ports and registers
`timescale 1ns/10ps
module ALU (Sel, CarryIn, A, B, Y);
input
[4:0] Sel;
input
CarryIn;
input
[7:0] A, B;
output
[7:0] Y;
reg
[7:0] Y;
reg
[7:0] LogicUnit, ArithUnit, ALU_NoShift;
always @(Sel or A or B or CarryIn)
begin
… the descriptions of different units come here …
end
endmodule
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study I
Arithmetical Logical Unit (ALU)
Logical Unit
Arithmetical Unit
case ({Sel[1:0]})
2'b00 : LogicUnit = A & B;
2'b01 : LogicUnit = A | B;
2'b10 : LogicUnit = A ^ B;
2'b11 : LogicUnit = ~A;
default : LogicUnit = 8'bX;
endcase
Do not forget to type { and } !!!
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case ({Sel[1:0], CarryIn})
3'b000 : ArithUnit = A;
3'b001 : ArithUnit = A + 1;
3'b010 : ArithUnit = A + B;
3'b011 : ArithUnit = A + B + 1;
3'b100 : ArithUnit = A + ~B;
3'b101 : ArithUnit = A - B;
3'b110 : ArithUnit = A - 1;
3'b111 : ArithUnit = A;
default : ArithUnit = 8'bX;
endcase
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study I
Arithmetical Logical Unit (ALU)
Multiplexer unit
Shifter Unit
if (Sel[2])
ALU_NoShift = LogicUnit;
else
ALU_NoShift = ArithUnit;
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case ({Sel[4:3]})
2'b00 : Y = ALU_NoShift;
2'b01 : Y = ALU_NoShift << 1;
2'b10 : Y = ALU_NoShift >> 1;
2'b11 : Y = 8'b0;
default : Y = 8'bX;
endcase
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study I
Arithmetical Logical Unit (ALU) Testbench
`timescale 1ns/10ps
module TESTGEN_ALU;
reg
[4:0] Sel;
reg
CarryIn;
reg
[7:0] A,B;
wire
[7:0] Y;
integer i;
ALU ALU(Sel, CarryIn, A, B, Y);
initial
begin
Sel = 5'b00000;
A = 8'h33;
B = 8'hcc;
CarryIn = 0;
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// Test Arithmetic Unit
for (i=0; i<4; i=i+1)
#10 Sel[1:0] = Sel[1:0] + 2'b01;
#10 CarryIn = 1;
for (i=0; i<4; i=i+1)
#10 Sel[1:0] = Sel[1:0] + 2'b01;
#10 CarryIn = 0;
// Test Logic Unit
#10 Sel[2] = 1;
for (i=0; i<4; i=i+1)
#10 Sel[1:0] = Sel[1:0] + 2'b01;
#10 Sel[2] = 0;
// Test Shift operations
for (i=0; i<4; i=i+1)
#10 Sel[4:3] = Sel[4:3] + 2'b01;
end
endmodule
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study I
You can find the ALU verilog source in the lab1 directory.
In this exercise you have to do these steps:
•
Create the ALU testbench
–
–
–
•
•
Check the arithmetical unit
Check the logical unit
Check the shifter unit
Compile, elaborate and simulate
Check the operation of the ALU
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Coffee break
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study II
Central Processor Unit (CPU)
The design of a processor is a complex scenario. Multimillion
instruction processors (MIPS), complex instruction set
processors (CISC), reduced instruction set processors (RISC)
are all models that are used in different applications.
The HDL description you will be working with is a simple
processor that does 4 simple mathematical functions.
The circuit implements addition, incrementing, complementing
and XOR.
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study II
The Verilog Lab modules
There are five modules used in this walkthrough:
alu.v
reg8.v
count5.v
decode.v
cpu.v
Contains the mathematical operations
Works as the random access memory (RAM)
Works as a program counter
Controls the flow of data through a state machine
Top-level design
The verilog description of the all models are completed.
The intention of this lab is creating a testbench and simulating
the top level design (CPU).
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case Study II
The schematic of CPU
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case Study II
The operation of the CPU
The CPU begins to operate on the positive edge of the reset.
At all positive edge of the clock signal the operation state of the
CPU changes. There are 8 states of the operation / cycle period
On reset signal the counter of the CPU resets, and set pcout
(address of instructions) to 00h – this is the address of the first
instruction. The value of the PC register is incremented per each
cycle
The ALU executes an instruction (which one is determined by
opcode) when ena is enabled.
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study II
module decode(ld_acc, mem_rd, mem_wr,
inc_pc, ld_pc, ld_ir, sel_dat, en_alu, sel_adr,
opcode, zero, clk, rst);
…
always @(posedge clk or negedge rst)
begin
if (!rst) state = 3'b000;
else
case (state)
3'b000:
state = 3'b001;
3'b001:
state = 3'b011;
3'b011:
state = 3'b010;
3'b010:
state = 3'b110;
3'b110:
state = 3'b111;
3'b111:
state = 3'b101;
3'b101:
state = 3'b100;
3'b100:
state = 3'b000;
endcase
end
….
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The decode module
determines the operation of
the CPU in different states
and determine the order of
the states.
1
0
3
The cycle of
states
4
5
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
7
6
2
Case study II
In the testbench imagine there is a RAM connected to the CPU
A operand is stored in the RAM on the 08h address, the B
operand is stored on the 09h address.
The instructions are stored from the 00h address.
memrd / 1
clock / 1
reset / 1
memwr / 1
CPU
address/ 5
0000
0100 – A operand
0101 – B operand
dataout / 8
RAM
datain / 8
1111
testbench
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study II
The instruction word format (8 bit)
ooo | aaaaa – MSB (3 bit) the operation code
– LSB (8 bit) the address of the operand,
which is stored in the instruction register
(IR) after has been read from the memory
Example:
100 | 01001 (89h) – Memory read (dataIn F0h) from 09h
– Generate accumulator XOR dataIn
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study II
case (state)
3'b000: {inc_pc, ld_acc, ld_pc,mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} =
9'b000000001
State 0 – set the address to pcout
3'b001: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} =
9'b000011001;
State 1 – read from memory, and load the
instruction to the IR
3'b011: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} =
9'b000000001;
State 3 – stop reading from the memory
3'b010: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} =
9'b100000001;
State 2 – increment PC
3'b110: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} =
9'b000000000;
State 6 – set the address to IR (for read
operand from the memory)
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study II
3'b111: case (opcode)
State 7 – depends on the opcode
3'b111: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} =
9'b001000010;
Opcode 7 - enable ALU, load IR address to PC
register (simple goto)
3'b010,
3'b100,
3'b101: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} =
9'b000010010;
Opcode 2,4,5 – enable ALU, enable mem_rd
3'b000: begin
{inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =
9'b000000010;
Opcode 0 – enable ALU
end
default: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =
9'b000000010;
Opcode 1,3,6 – enable ALU
endcase
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study II
3'b101: case (opcode)
State 5 – depends on the opcode
3'b001: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =
9'b000000100;
Opcode 1 - enable sel_dat
3'b010,
3'b100,
3'b101: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =
9'b010000000;
Opcode 2,4,5 – enable ld_acc (Load to
accumulator)
3'b000: begin
{inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =
9'b000000100;
Opcode 0 – enable sel_dat
end
default: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =
9'b000000100;
Opcode 3,6,7 – enable sel_dat
endcase
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study II
3'b100: case (opcode)
State 4 – depends on the opcode
3'b110: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =
9'b000100100;
Opcode 6 - enable sel_dat, mem_wr
3'b010,
3'b100,
3'b101: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =
9'b000000000;
Opcode 2,4,5 – disable all
3'b000: begin
{inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =
9'b000000100;
Opcode 0 – enable sel_dat
end
default: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =
9'b000000100;
Opcode 3,6,7 – enable sel_dat
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study II
You can find the CPU verilog sources in the lab2 directory.
In this exercise you have to do these steps:
•
Create the CPU testbench
–
–
–
•
•
Read two operands from the memory
(from the 16h and 17h address)
Generate A and B
Write the result to the 1Ch address
Compile, elaborate and simulate
Check the operation of CPU
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Coffee break
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Delay backannotation
In the next few pages, you will become familiar with the
verilog backannotation interface. The presentation that
follows lets you experiment with simulation of the correct
physical delays.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Delay backannotation
Standard Delay File (SDF)
After the Verilog RTL description is generated by any Physical
Synthesis (e.g. Cadence PKS) or Physical Design Tool (e.g.
Silicon Ensemble) the real constraints of the physical design
generated in a SDF file.
The SDF file contains the pre-calculated or the real delays of
each nets (RC) and the delays of each blocks (gates).
This file can be loaded into the Verilog Simulator Environment,
so the pre-calculated or real, accurate timing rule violation can
be viewed and checked.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Delay backannotation
To enable the SDF elaborating:
Select ToolsElaborator
menu item
and
Click on Advanced Options
button, then the Elaborator
Advanced Options windows
appears
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Delay backannotation
Select Verilog
Perfomance tab,
and check in
Delay Mode and
select path mode
Select PLI tab,
and check in
Enable delay
annotation at
simulation time
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Delay backannotation
Select
Annotation and
check in Specify
delay types and
select Maximum
mode
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Delay backannotation
The Verilog RTL source simulation result, without using SDF file
(the 0.1ns - the default delay of the gates - can be seen)
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Delay backannotation
timescale 1ns/10ps
module test_alu;
reg clk, ena, rst;
wire [7:0] aluout;
parameter half_cyc = 100;
alu alu(aluout, zero, opcode, data, accum, clk, ena, rst);
…
initial $sdf_annotate("alu_rtl.sdf",alu);
…
initial
begin
Type into the testbench source initial to use SDF in the
….
elaboration and in the simulation:
end
$sdf_annotate(“sdf_file_name.sdf”,module_name)
…
endmodule Should be the first initial before the other initials !!!
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Delay backannotation
The Verilog RTL source simulation result with using SDF file
(the 1.4ns - the delays of the nets and the gates)
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study III
You can find the CPU verilog sources, technology library files
and the .sdf file in the lab3 directory.
In this exercise you have to do these steps:
•
Use the recently generated CPU testbench
•
Compile
•
Elaborate using .sdf file
•
Simulate
•
Check the operation of CPU
•
Compare delays with original one
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Full Break!
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory